Transmission, storage or processing of digital signals is most commonly performed with the aid of signal formats in which the data element, either a digital value or a change in digital value, is represented by the occurrence or absence at a pre-defined position in time of a signal. The signal may, for example, be a pulse or a transition. The signal positions in time are defined with reference to regular clock signals or, in other words, as the relative phase there between. Many of the commonly used signal formats are self-clocking, which is to say they lack dedicated clock signals and, instead, the clock information is conveyed by the data signal sequence itself.
For correct extraction of the data information conveyed by the digital signals the correct phase relationship between the clock signals and the data signals is essential. In the course of transmission, this phase relationship may, however, be degraded as may be the shape and magnitude of the digital signals. The main causes, among others, of signal degradation are noise, dispersion and bandwidth restrictions on the transmission channel, and the signal needs to be restored prior to, for example, processing, error correction or, especially in long distance telecommunications systems, onward transmission from a repeater or regenerator.
Conventionally the restoration of the correct signal timing has been accomplished by extracting the clock signals from the digital signal sequence, and applying the recovered clock signals to clock the data signals through an appropriate gate. A variety of methods exist for performing the clock signal extraction, such as, for example, passive extraction with the aid of appropriate filters, or active extraction with phase-lock loops employing voltage controlled oscillators. In order for the clock signal to be applied to the gate with the correct phase relative to the data signal it is necessary to compensate for signal delays in the clock extraction circuits. Heretofore, compensation has conventionally been achieved by providing a delay line, such as a co-axial delay line, between the clock extraction circuit and the gate. As the delay in the clock extraction circuit varies from circuit to circuit, such delay lines have to be individually matched to each circuit during manufacture. Not only is this time-consuming and costly in terms of labour, but also no facility exists to compensate for the effect of short term temperature variations, long term ageing effects, and the like.
Timing recovery circuits for repeaters, their requirements and conventional solutions thereto, are conveniently summarised in R. L. Rosenber et al. "Optical Fiber Repeatered Transmission Systems Utilizing SAW Filters", Proc. IEEE Ultrasonics Symposium 1982, Vol.1 pp238-246.
It is an object of the present invention to provide a timing control circuit which avoids, or at least mitigates some of the aforementioned shortcomings of the conventional techniques.
It is another object of the present invention to provide an improved signal retiming circuit for digital signals.
According to one aspect of the present invention, a retiming circuit for digital signals comprises means to derive timing signals, phase adjusting means to adjust the phase of the timing signals, gating means to gate digital signals with the phase adjusted timing signals to generate re-timed digital signals, and means to control the phase adjusting means including negative feedback means responsive to the phase difference between the timing signals and the digital signals. The phase difference between timing and digital signals is conveniently measured by detecting the phase difference between the digital signals and the re-timed digital signals.
Preferably, the feedback means are responsive also to a reference signal.
The timing signals may be regular clock signals. The clock signals may be obtained by extraction from the digital signals. The extraction may be passive using, for example, filters such as surface acoustic wave (SAW) filters, which isolate the clock signal component of the digital signals; or extraction may be active using, for example, phase-lock loops provided with variable frequency oscillators running in synchronism with the clock signal component of the digital signals.
Alternatively, the timing signals may be a second sequence of digital signals differing from said digital signals in phase. The present invention may then be employed to synchronize the phases of, or compare, two nominally identical signal sequences.
According to a further aspect of the present invention, a regenerator for a long distance digital telecommunications system includes a re-timing circuit for received digital signals, means to generate a local clock signal sequence of a frequency commensurate with the clock frequency of the received digital signals, phase adjusting means to adjust the phase of the local clock generating means, a re-timing gate to gate the received digital signals with the local clock signals so as to provide re-timed digital signals, and means to control the clock signal phase adjusting means, wherein the control means comprise a negative feedback loop to maintain the phase relationship between the clock signals and the re-timed data signals at a value determined by a reference signal. The means for adjusting the phase of the timing signals or the clock signals conveniently comprise a phase shifter.
The relative timing or phase difference, of the (un-retimed) digital signals or the clock signals, and the re-timed digital signals may be sensed with a phase detector circuit. The phase detector may be of a conventional type. However, where the phase difference between the un-retimed and the re-timed digital signals is employed then, as the retimed digital signals are always delayed relative to the un-retimed signals and no ambiguity can therefore arise as to their sequence in time, the phase detector may conveniently operate over 4.pi. radians of phase angle rather than being restricted to the usual 2.pi. radians of phase angle.
The reference signal may be provided by a controlled current or voltage source. Preferably, however, at least one component of the reference signal is generated from the digital signals. This may be accomplished, for example, by employing a fixed delay line of arbitrary delay time, feeding the sequence of digital signals together with the same sequence of digital signals delayed in that delay line to a further phase-detector circuit, and integrating over time the output signal of the phase detector circuit.